The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Nov. 08, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Jawad B. Khan, Portland, OR (US);

Jorge Ulises Martinez Araiza, Beaverton, OR (US);

Michael D. Nelson, Mountain View, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01R 12/00 (2006.01); H05K 1/00 (2006.01); H01R 12/70 (2011.01); H01R 12/72 (2011.01); H05K 7/14 (2006.01); H01R 43/20 (2006.01); H01R 13/26 (2006.01);
U.S. Cl.
CPC ...
H01R 12/7005 (2013.01); H01R 12/725 (2013.01); H01R 13/26 (2013.01); H01R 43/20 (2013.01); H05K 7/1487 (2013.01);
Abstract

Embodiments of the present disclosure are directed towards a connector for a memory device in a computing system. In one embodiment, the connector includes a housing having a cavity to receive a mating end of a printed circuit board (PCB). The cavity includes first groups of first contacts arranged along an inside wall of the cavity, to engage with respective second groups of second contacts arranged around the mating end of the PCB. The cavity further includes a bar disposed inside the cavity to bridge the cavity, to receive a notch formed on the mating end of the PCB. A depth of the notch defines a number of the first groups of first contacts to be engaged with a respective number of the second groups of second contacts on the mating end of the PCB.


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