The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Oct. 19, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

June-Hong Park, Seongnam-si, KR;

Bong-Soon Lim, Seoul, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); H01L 27/11529 (2017.01); G11C 16/08 (2006.01); H01L 27/11519 (2017.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/11573 (2017.01); H01L 27/11524 (2017.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11529 (2013.01); G11C 16/08 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11582 (2013.01); G11C 16/0483 (2013.01);
Abstract

A nonvolatile memory device includes a plurality of gate lines extending in a first direction and stacked in a second direction to form a memory block, where the second direction is perpendicular to the first direction, an address decoder disposed at a first side of the plurality of gate lines to drive the plurality of gate lines, a voltage compensation line extending in the first direction substantially in parallel with the plurality of gate lines, and overlapping with a target gate line among the plurality of gate lines in the second direction, a rising vertical contact extending in the second direction to connect the address decoder and a first portion of the voltage compensation line, and conduction paths connecting in the second direction the first and second portions of the voltage compensation line with near and far end portions of the target gate line.


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