The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Mar. 05, 2015
Applicant:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Inventors:

Kenji Meguro, Nagano, JP;

Taishi Wakabayashi, Nagano, JP;

Norihiro Kobayashi, Takasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/762 (2006.01); B32B 7/12 (2006.01); B32B 9/04 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76251 (2013.01); B32B 7/12 (2013.01); B32B 9/04 (2013.01); H01L 21/02233 (2013.01); H01L 21/02532 (2013.01); H01L 21/02595 (2013.01); H01L 21/30625 (2013.01); B32B 2250/02 (2013.01); B32B 2255/20 (2013.01); B32B 2307/206 (2013.01); B32B 2457/14 (2013.01);
Abstract

A bonded SOI wafer is manufactured by bonding a bond and a base wafer, each composed of a silicon single crystal, via an insulator film, depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; wherein, the base wafer is a silicon single crystal wafer having a resistivity of 100 Ω·cm or more, depositing the polycrystalline silicon layer further includes a stage for previously forming an oxide film on the surface of the base wafer on which the polycrystalline silicon layer is deposited, and the polycrystalline silicon layer is deposited at a temperature of 900° C. or more.


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