The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Apr. 09, 2019
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Tetsuya Arai, Kanagawa, JP;

Junki Taniguchi, Kanagawa, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/40 (2006.01); H03K 19/177 (2006.01); G11C 11/4093 (2006.01); H03H 11/28 (2006.01); G11C 11/4096 (2006.01); H03K 19/00 (2006.01); H03K 3/037 (2006.01); H03K 19/094 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 11/4096 (2013.01); H03H 11/28 (2013.01); H03K 3/0372 (2013.01); H03K 19/0013 (2013.01); H03K 19/09425 (2013.01); H03K 19/17772 (2013.01); H03K 19/17784 (2013.01);
Abstract

Disclosed herein is an apparatus that includes: a data terminal; a first output transistor connected between the data terminal and a first power line supplying a first power potential; a first tristate circuit including an output node connected to a control electrode of the first output transistor, a first pull-up transistor configured to drive the output node to a first logic level, and a first pull-down transistor configured to drive the output node to a second logic level; and a second tristate circuit including an output node connected to the control electrode of the first output transistor, a second pull-up transistor configured to drive the output node to the first logic level, and a second pull-down transistor configured to drive the output node to the second logic level. The second pull-up and pull-down transistors have a different threshold voltage from the first pull-up and pull-down transistors.


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