The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Dec. 18, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Rameet Pal, New Delhi, IN;

Taranjit Singh Kukal, Delhi, IN;

Rajesh Prasad Singh, Uttar Pradesh, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06T 11/60 (2006.01); G06F 3/0484 (2013.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01); G06F 3/04842 (2013.01); G06F 17/505 (2013.01); G06F 17/5031 (2013.01); G06T 11/60 (2013.01);
Abstract

Embodiments include herein are directed towards a method for generating an input/output model from a SPICE (Simulation Program with Integrated Circuit Emphasis) netlist. Embodiments may include receiving, using a processor, a SPICE netlist associated with an electronic design and selecting at least a portion of the SPICE netlist for analysis. Embodiments may further include reading the selected portion of the SPICE netlist and rendering a schematic symbol corresponding to the selected portion of the netlist. Embodiments may also include performing one or more operations associated with the schematic symbol and translating the one or more operations into simulation commands.


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