The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 07, 2020

Filed:

Dec. 29, 2015
Applicant:

Arteris, Inc., Campbell, CA (US);

Inventors:

Monica Tang, San Jose, CA (US);

Xavier van Ruymbeke, Issy les Moulineaux, FR;

Assignee:

ARTERIS, INC., Campbell, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03M 13/00 (2006.01); G06F 11/10 (2006.01); H03M 13/29 (2006.01); H03M 13/35 (2006.01); G11C 29/52 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); H03M 13/2906 (2013.01); H03M 13/356 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.


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