The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Aug. 20, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Alexei Sadovnikov, Sunnyvale, CA (US);

Doug Weiser, Plano, TX (US);

Mattias Erik Dahlstrom, Los Altos, CA (US);

Joel Martin Halbert, Tucson, AZ (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/808 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 21/324 (2006.01); H01L 23/535 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66916 (2013.01); H01L 21/265 (2013.01); H01L 21/324 (2013.01); H01L 23/535 (2013.01); H01L 29/1058 (2013.01); H01L 29/1066 (2013.01); H01L 29/808 (2013.01); H01L 29/8086 (2013.01); H01L 29/0692 (2013.01);
Abstract

A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.


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