The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Dec. 07, 2016
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Sergio A. Ajuria, Austin, TX (US);

Phuc M. Nguyen, Austin, TX (US);

Douglas M. Reber, Austin, TX (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/482 (2006.01); H01L 23/485 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 23/3114 (2013.01); H01L 23/485 (2013.01); H01L 23/4824 (2013.01); H01L 23/5223 (2013.01); H01L 24/02 (2013.01); H01L 24/12 (2013.01); H01L 24/13 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13024 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.


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