The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Feb. 23, 2018
Applicant:

Globalfoundries Singapore Pte. Ltd., Singapore, SG;

Inventors:

Yongtian Hou, Singapore, SG;

Khee Yong Lim, Singapore, SG;

Ming-Tsang Tsai, Singapore, SG;

Elgin Kiok Boone Quek, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 49/02 (2006.01); H01L 29/51 (2006.01); H01L 29/78 (2006.01); H01L 27/108 (2006.01); H01L 21/768 (2006.01); H01L 27/11507 (2017.01); H01L 29/423 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 28/56 (2013.01); H01L 21/76877 (2013.01); H01L 27/10852 (2013.01); H01L 27/11507 (2013.01); H01L 29/40111 (2019.08); H01L 29/4232 (2013.01); H01L 29/516 (2013.01); H01L 29/78391 (2014.09);
Abstract

Methods for producing FETs with negative capacitance and the resulting device are disclosed. Embodiments include forming a gate stack over a semiconductor substrate by: forming a gate oxide over the semiconductor substrate; forming a first metal gate electrode over the gate oxide; forming a dummy gate over the metal gate electrode; and forming sidewall spacers on first and second sides of the gate stack; forming an ILD over the substrate and gate stack; removing the dummy gate and at least a portion of sidewall spacers to form an opening; forming a ferro-electric (FE) layer in the opening; and forming a second metal gate electrode over the FE layer.


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