The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Aug. 30, 2018
Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

Emmanuel Gourvest, Voiron, FR;

Yannick Le Friec, Le Cheylas, FR;

Laurent Favennec, Villard Bonnot, FR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); H01L 27/2472 (2013.01); H01L 45/1206 (2013.01); H01L 45/1226 (2013.01); H01L 45/1683 (2013.01); H01L 45/06 (2013.01); H01L 45/126 (2013.01); H01L 45/1233 (2013.01); H01L 45/144 (2013.01); H01L 45/16 (2013.01);
Abstract

Two phase-change memory cells are formed from a first conductive via, a second conductive and a central conductive via positioned between the first and second conductive vias where a layer of phase-change material is electrically connected to the first and second conductive vias by corresponding resistive elements and insulated from the central conductive via by an insulating layer. The conductive vias each include a lower portion made of a first metal (such as tungsten) and an upper portion made of a second metal (such as copper). Drains of two transistors are coupled to the first and second conductive vias while sources of those two transistors are coupled to the central conductive via.


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