The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2019
Filed:
Feb. 17, 2018
Varian Semiconductor Equipment Associates, Inc., Gloucester, MA (US);
Baonian Guo, Andover, MA (US);
Qintao Zhang, Gloucester, MA (US);
VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC., Gloucester, MA (US);
Abstract
Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.