The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Aug. 01, 2016
Applicants:

Young Hee Song, Seongnam-si, KR;

Hyouk Lee, Cheonan-si, KR;

Ki Hong Song, Seoul, KR;

Jun Hee Jeong, Yongin-si, KR;

Inventors:

Young Hee Song, Seongnam-si, KR;

Hyouk Lee, Cheonan-si, KR;

Ki Hong Song, Seoul, KR;

Jun Hee Jeong, Yongin-si, KR;

Sung Sik Yun, Seoul, KR;

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/10 (2006.01); H01L 25/065 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/105 (2013.01); H01L 25/0657 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/32 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 2224/0331 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49176 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06562 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1052 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/37001 (2013.01);
Abstract

The semiconductor package according to the present invention comprises: an integrated substrate; a bottom chip stack, which is mounted on the integrated substrate, has multiple memory semiconductor dies stacked chip-on-chip, and takes charge of a part of the whole memory capacity; at least one top chip stack, which is mounted on the bottom package, has multiple memory semiconductor dies mounted therein, and takes charge of the rest of the whole memory capacity; an integration wire for electrically connecting the bottom chip stack and the top chip stack(s); and an integration protection member for sealing the integration wire.


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