The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 31, 2019
Filed:
Dec. 06, 2017
Applicant:
Nxp Usa, Inc., Austin, TX (US);
Inventors:
Yi Yin, Munich, DE;
Ziqiang Tong, Ottobrunn, DE;
Assignee:
NXP USA, Inc., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/522 (2006.01); H01L 23/66 (2006.01); H01L 21/56 (2006.01); H01L 23/64 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5227 (2013.01); G06F 17/5068 (2013.01); G06F 17/5081 (2013.01); H01L 21/56 (2013.01); H01L 23/645 (2013.01); H01L 23/66 (2013.01); G06F 2217/40 (2013.01); G06F 2217/82 (2013.01); G06F 2217/84 (2013.01);
Abstract
A method of tuning inductive and/or capacitive components within an integrated circuit device. The method comprises measuring bare-die mounted performance of such a component formed within a semiconductor die, determining a package distribution layer pattern for the at least one component for achieving a desired performance for the at least one component based at least partly on the measured bare-die mounted performance, and packaging the semiconductor die with the determined package distribution layer pattern for the at least one component.