The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

May. 16, 2017
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Chun-Yi Cheng, Hsinchu, TW;

Wei-Yuan Cheng, Hsinchu County, TW;

Shu-Wei Kuo, Hsinchu County, TW;

Yu-Jhen Yang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); H01L 21/02 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3107 (2013.01); H01L 21/02172 (2013.01); H01L 21/4846 (2013.01); H01L 21/76832 (2013.01); H01L 21/76838 (2013.01); H01L 24/11 (2013.01); H01L 24/12 (2013.01); H01L 2224/05008 (2013.01); H01L 2224/05022 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01022 (2013.01);
Abstract

A package structure includes a redistribution layer, a chip, an encapsulant, a plurality of under ball release layers, and a plurality of solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface, and a patterned circuit layer, wherein the patterned circuit layer includes a plurality of pads protruding from the first surface. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface and encapsulates the chip. The under ball release layers cover the pads respectively. The solder balls are disposed on the under ball release layers and electrically connected to the pads.


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