The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Sep. 17, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Hyunchul Lee, Hwaseong-si, KR;

Yunseung Kang, Seoul, KR;

Sounghee Lee, Hwaseong-si, KR;

Jiseung Lee, Seoul, KR;

Sanggyo Chung, Anyang-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3213 (2006.01); H01L 21/033 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 21/32139 (2013.01); H01L 21/0337 (2013.01); H01L 21/3086 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01);
Abstract

Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.


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