The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 31, 2019

Filed:

Dec. 29, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David B. Carlton, Oakland, CA (US);

Xin Guo, San Jose, CA (US);

Yu Du, Santa Clara, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/061 (2013.01); G06F 3/0659 (2013.01);
Abstract

Provided are an apparatus, system and method for apparatus, system and method for throttling an acceptance rate for adding host Input/Output (I/O) commands to a buffer in a non-volatile memory storage device. Information is maintained on an input rate at which I/O commands are being added to the buffer and information is maintained on an output rate at which I/O commands are processed from the buffer to apply to execute against the non-volatile memory. A determination is made of a current level of available space in the buffer and an acceptance rate at which I/O commands are added to the buffer from the host system to process based on the input rate, the output rate, the current level of available space, and an available space threshold for the buffer to maintain the buffer at the available space threshold. I/O commands are added to the buffer to process based on the acceptance rate. The I/O commands are accessed from the buffer to process to execute against the non-volatile memory.


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