The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Feb. 01, 2018
Applicant:

Silanna Uv Technologies Pte Ltd, Singapore, SG;

Inventors:

Liam Anderson, Wentworth Point, AU;

William Lee, West Ryde, AU;

William Schaff, Brisbane, AU;

Johnny Cai Tang, Baulkham Hills, AU;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 33/06 (2010.01); H01L 33/32 (2010.01); H01L 33/12 (2010.01);
U.S. Cl.
CPC ...
H01L 33/06 (2013.01); H01L 33/12 (2013.01); H01L 33/32 (2013.01);
Abstract

A dislocation filter for a semiconductor device has a buffer layer comprising a short-period superlattice (SPSL) layer. The SPSL layer has first sub-layers of a first material that alternate with second sub-layers of a second material, the first material and the second material being group III-N binary materials that are different from each other. Each of the first sub-layers and each of the second sub-layers has a sub-layer thickness less than or equal to 12 monolayers. The buffer layer also includes a third layer of a third material, the third material being a group III-N material. The SPSL forms a sandwich structure with the third layer. The buffer layer bends dislocations away from a growth direction of the buffer layer.


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