The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Dec. 27, 2017
Applicant:

National Taiwan Normal University, Taipei, TW;

Inventors:

Chun-Hu Cheng, Tainan, TW;

Chun-Yen Chang, Zhubei, TW;

Yu-Chien Chiu, Kaohsiung, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1159 (2017.01); H01L 29/78 (2006.01); H01L 27/11587 (2017.01); H01L 27/11597 (2017.01); H01L 29/792 (2006.01); G11C 16/04 (2006.01); H01L 27/11565 (2017.01); H01L 27/1157 (2017.01); H01L 27/11578 (2017.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1159 (2013.01); G11C 11/223 (2013.01); G11C 16/0483 (2013.01); H01L 27/1157 (2013.01); H01L 27/11565 (2013.01); H01L 27/11578 (2013.01); H01L 27/11587 (2013.01); H01L 27/11597 (2013.01); H01L 29/78391 (2014.09); H01L 29/792 (2013.01);
Abstract

A flash memory structure and a method of making the same are provided. The flash memory structure comprises a substrate, a source, a drain, a tunnel isolation layer, a ferroelectric-charge-trapping layer, at least one blocking isolation layer and at least one gate. The substrate is made of a semiconductive material. The source is formed on the substrate. The drain is formed on the substrate and spaced apart from the source. The tunnel isolation layer is formed on the substrate. The ferroelectric-charge-trapping layer is formed on the tunnel isolation layer and contains a charge-trapping layer and a ferroelectric negative-capacitance effect layer. The at least one blocking isolation layer is formed on the ferroelectric-charge-trapping layer. The at least one gate is formed on the blocking isolation layer. The ferroelectric negative-capacitance effect layer is made of a material with the ferroelectric negative-capacitance effect.


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