The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Jul. 12, 2018
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Wei Cheng Wu, Zhubei, TW;

Chien-Hung Chang, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11575 (2017.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11575 (2013.01); H01L 29/0649 (2013.01);
Abstract

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a logic region having a plurality of transistor devices disposed within a substrate, an embedded memory region having a plurality of memory devices disposed within the substrate, and a boundary region separating the logic region from the embedded memory region. The boundary region includes a first isolation structure having a first upper surface and a second upper surface below the first upper surface. The first and second upper surfaces are coupled by an interior sidewall overlying the first isolation structure. The boundary region further includes a memory wall arranged on the second upper surface and surrounding the embedded memory region, and a logic wall arranged on the first upper surface and surrounding the memory wall. The logic wall has an upper surface that is above the plurality of memory devices and the memory wall.


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