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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10515817 B1

PDFFull Text
Date of Patent:
Dec. 24, 2019

Filed:

Jul. 06, 2018

Method for forming features of semiconductor structure having reduced end-to-end spacing

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Xi-Zong Chen, Tainan, TW;

Yun-Yu Hsieh, Hsinchu, TW;

Cha-Hsin Chao, Taipei, TW;

Li-Te Hsu, Shanhua Township, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater & Matsil, LLP

Primary Examiner:

Allan W Olsen

Int. Cl.
CPC ...
H01L 21/308 (2006.01); H01L 21/768 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01J 37/00 (2006.01); H01L 21/3213 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 21/3086 (2013.01); H01J 37/00 (2013.01); H01L 21/0337 (2013.01); H01L 21/0338 (2013.01); H01L 21/3088 (2013.01); H01L 21/31116 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/32134 (2013.01); H01L 21/32155 (2013.01);
Abstract

A method includes forming a mask layer over a target layer. A first etching process is performed on the mask layer to form a first opening and a second opening in the mask layer. A second etching process is performed on the mask layer to reduce an end-to-end spacing between the first opening and the second opening. The first etching process and the second etching process have different anisotropy properties. A pattern of the mask layer is transferred to the target layer.

Find Patent Forward Citations

Chen, Xi-Zong. (2019). Method for forming features of semiconductor structure having reduced end-to-end spacing (U.S. Patent No. 10515817). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10515817

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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