The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Aug. 31, 2018
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Agostino Macerola, San Benedetto dei Marsi, IT;

Marco-Domenico Tiburzi, Avezzano, IT;

Stefano Perugini, Popoli, IT;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/14 (2006.01); G05F 3/16 (2006.01); G06F 1/3203 (2019.01); G06F 1/3234 (2019.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 5/145 (2013.01); G05F 3/16 (2013.01); G06F 1/3203 (2013.01); G06F 1/3275 (2013.01); G11C 5/147 (2013.01); G11C 16/30 (2013.01); G11C 16/0458 (2013.01); G11C 16/0483 (2013.01);
Abstract

Voltage generation circuits include a stage including a voltage driver having inputs connected to respective voltage nodes and a clock signal, and a stage capacitance having a first electrode connected to an output of the voltage driver and a second electrode connected to a voltage isolation device. The voltage driver might be configured to connect its output to receive a first voltage when the clock signal has a particular logic level and a voltage level of its output is less than a threshold, to connect its output to receive a second voltage greater than the first voltage when the clock signal has the particular logic level and the voltage level of its output is greater than the threshold, and to connect its output to receive a third voltage less than the first voltage when the clock signal has a different logic level.


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