The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Jun. 29, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Roland Ruehl, San Carlos, CA (US);

Henry Yu, Palo Alto, CA (US);

Joshua Alexander Baudhuin, Portland, OR (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/50 (2013.01); G06F 17/5036 (2013.01); G06F 17/5072 (2013.01); G06F 17/5081 (2013.01); G06F 17/509 (2013.01); G06F 17/5045 (2013.01); G06F 17/5068 (2013.01); G06F 2217/06 (2013.01);
Abstract

Disclosed are techniques for implementing routing aware floorplanning or placement for an electronic design. These techniques preprocess an electronic design and a plurality of inputs for a floorplanner or placer, identify a tentative location for inserting a block comprising one or more pins into a floorplan or placement layout, snap the block to a legal location based at least in part upon one or more characteristics of the one or more pins or one or more pseudo-pins, and update the floorplan or placement layout with one or more geometric routes based in part or in whole upon the legal location.


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