The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2019
Filed:
Jul. 01, 2016
Intel Corporation, Santa Clara, CA (US);
Zhiming Li, Shanghai, CN;
Xingping Ruan, Shanghai, CN;
Xiao Hu, Shanghai, CN;
Terrence Trausch, Portland, OR (US);
Robert Pebly, Beaverton, OR (US);
Xiang Zhou, Shanghai, CN;
Jie Yan, Shanghai, CN;
Intel Corporation, Santa Clara, CA (US);
Abstract
A system includes a host processor () and a peripheral device (). The host processor () is coupled to the peripheral device () by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device () can include logic circuitry to identify, based on an application using the device and the host processor (), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (). The host processor () comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.