The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 24, 2019
Filed:
Mar. 29, 2018
Applicant:
Rambus Inc., Sunnyvale, CA (US);
Inventors:
Trung Diep, San Jose, CA (US);
Eric Linstadt, Palo Alto, CA (US);
Assignee:
Rambus Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/02 (2006.01); G06F 12/08 (2016.01); G06F 12/126 (2016.01); G06F 12/0891 (2016.01); G06F 12/1009 (2016.01); G06F 3/06 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0284 (2013.01); G06F 3/0616 (2013.01); G06F 3/0647 (2013.01); G06F 3/0673 (2013.01); G06F 12/08 (2013.01); G06F 12/0891 (2013.01); G06F 12/1009 (2013.01); G06F 12/126 (2013.01); G06F 12/0246 (2013.01); G06F 2212/1036 (2013.01); G06F 2212/7211 (2013.01);
Abstract
Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling function and a memory address mapping function. Upon receipt of a page fault, the page fault handling function maps an evicted virtual memory address to a stressed page and maps a stressed virtual memory address to a free page using the memory address mapping function.