The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 24, 2019

Filed:

Dec. 27, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Robert F. Kwasnick, Palo Alto, CA (US);

Huy Le, San Jose, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B60W 50/02 (2012.01); G06F 11/00 (2006.01); B60R 16/023 (2006.01); G05D 1/00 (2006.01); F02D 41/26 (2006.01); G06F 7/00 (2006.01); B60W 10/119 (2012.01); G07C 5/00 (2006.01); G07C 5/08 (2006.01); B60W 50/029 (2012.01);
U.S. Cl.
CPC ...
B60W 50/0205 (2013.01); G05D 1/00 (2013.01); G05D 1/0088 (2013.01); G07C 5/008 (2013.01); G07C 5/0816 (2013.01); B60W 2050/0215 (2013.01); B60W 2050/0292 (2013.01);
Abstract

Various systems and methods for monitoring integrate circuits for failure are described herein. A system to monitor for potential component failure includes a sensor array interface to obtain a first safety level from a first sensor and a second safety level from a second sensor, the first and second sensors installed in a machine, the first and second safety levels indicating how safe the machine is to operate; and a processor to: obtain configuration parameters from a rule data store; combine the first and second safety levels using the configuration parameters to produce a composite safety level; and initiate a responsive action based on the composite safety level.


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