The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2019
Filed:
May. 24, 2019
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO,. LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11568 (2017.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11568 (2013.01); H01L 21/31111 (2013.01); H01L 21/31144 (2013.01); H01L 21/32133 (2013.01); H01L 29/40117 (2019.08); H01L 29/42344 (2013.01); H01L 29/4983 (2013.01); H01L 29/513 (2013.01); H01L 29/518 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53261 (2013.01);
Abstract
A method for forming a semiconductor memory device structure includes forming a select gate structure and a dielectric layer, forming a charge trapping layer along a sidewall of a lower portion of the select gate structure and a sidewall of the dielectric layer, and forming a memory gate structure over the charge trapping layer. The select gate structure and the memory gate structure contact opposing sidewalls of the charge trapping layer. The dielectric layer is interposed between the charge trapping layer and the select gate structure.