The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 17, 2019
Filed:
Nov. 29, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Tzu-Chan Weng, Kaohsiung, TW;
Wan-Chun Kuan, Hsin-Chu, TW;
Yi-Wei Chiu, Kaohsiung, TW;
Meng-Je Chuang, Hsin-Chu, TW;
Assignee:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/67 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823481 (2013.01); H01L 21/31055 (2013.01); H01L 21/31116 (2013.01); H01L 21/67069 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01);
Abstract
A method of manufacturing a semiconductor device includes forming a semiconductor strip protruding above a substrate, forming isolation regions on opposing sides of the semiconductor strip, recessing the isolation regions in a first chamber using a first etching process, and increasing a planarity of the isolation regions in the first chamber using a second etching process.