logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10510606 B1

PDFFull Text
Date of Patent:
Dec. 17, 2019

Filed:

Apr. 26, 2019

Protected chip-scale package (csp) pad structure

Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yueh-Chuan Lee, Hsinchu, TW;

Chia-Chan Chen, Zhubei, TW;

Ching-Heng Liu, Miaoli, TW;

Assignee:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Attorney:

Eschweiler & Potashnik, LLC

Primary Examiner:

Douglas M Menz

Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/82 (2006.01); H01L 21/66 (2006.01); B23K 20/00 (2006.01); H01L 23/12 (2006.01); B23K 1/00 (2006.01); B23K 1/008 (2006.01); B23K 1/20 (2006.01); B23K 3/06 (2006.01); B23K 3/08 (2006.01); H01L 23/31 (2006.01); H01L 27/144 (2006.01); B23K 101/42 (2006.01);
U.S. Cl.
CPC ...
H01L 21/82 (2013.01); B23K 1/008 (2013.01); B23K 1/0016 (2013.01); B23K 1/20 (2013.01); B23K 3/0623 (2013.01); B23K 3/08 (2013.01); B23K 20/007 (2013.01); H01L 22/14 (2013.01); H01L 22/20 (2013.01); H01L 22/32 (2013.01); H01L 23/12 (2013.01); H01L 23/3114 (2013.01); H01L 27/144 (2013.01); H01L 27/14603 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14687 (2013.01); B23K 2101/42 (2018.08); H01L 27/1464 (2013.01); H01L 27/14625 (2013.01); H01L 2224/11 (2013.01);
Abstract

A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.

Find Patent Forward Citations

Loading…