The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Aug. 31, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Artur Antonyan, Suwon-si, KR;

Suk-soo Pyo, Hwaseong-si, KR;

Assignee:

Samsung Electronics Co., Ltd, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/16 (2006.01); G11C 13/00 (2006.01); H01L 43/08 (2006.01); G11C 7/04 (2006.01); G11C 7/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/1673 (2013.01); G11C 7/04 (2013.01); G11C 11/1655 (2013.01); G11C 11/1657 (2013.01); G11C 11/1697 (2013.01); G11C 13/004 (2013.01); H01L 43/08 (2013.01); G11C 7/08 (2013.01); G11C 2013/0054 (2013.01);
Abstract

Provided is a resistive memory device configured to output a value stored in a memory cell in response to a read command, the resistive memory device including a cell array including the memory cell and a reference cell; a reference resistance circuit configured to be electrically connected to the reference cell; an offset current source circuit configured to add or draw an offset current to or from a read current provided to the reference resistance circuit; and a control circuit configured to control the offset current source circuit to compensate for a variation of a resistance of the memory cell.


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