The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Oct. 26, 2016
Applicant:

Taiwan Semiconductor Manufacturing, Co., Ltd., Hsinchu, TW;

Inventors:

Wan-Ru Lin, Taipei, TW;

Ching-Shun Yang, Zhudong Township, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); G06F 2217/12 (2013.01); Y02P 90/265 (2015.11);
Abstract

The present disclosure is directed to systems and methods for cell placement. In embodiments, the methods include placing a plurality of cells selected from a cell library in a chip design to produce a first cell placement and determining whether the first cell placement satisfies design demands. In further embodiments, the method also includes rearranging a first cell to abut the first cell with a second cell when the first cell placement fails to satisfy design demands. In still further embodiments, the first cell is rearranged until a second cell placement providing a minimum metal route between the first and second cells is determined. In various embodiments, the method further includes generating a design layout based on the second cell placement and outputting the design layout to a machine readable storage medium. The outputted layout is used to manufacture a set of masks used in chip fabrication processes.


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