The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 17, 2019

Filed:

Aug. 28, 2017
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Yi-Xiao Ding, Austin, TX (US);

Zhuo Li, Austin, TX (US);

Wen-Hao Liu, Cedar Park, TX (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 1/10 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5031 (2013.01); G06F 1/10 (2013.01); G06F 17/5036 (2013.01); G06F 17/5077 (2013.01); G06F 2217/84 (2013.01);
Abstract

Systems, methods, media, and other such embodiments are described for routing track assignment in a circuit design. One embodiment involves accessing routing data for a circuit design, and a first wire of a plurality of wires in the routing data. A second wire is identified that is related to the first wire as a parent wire along a shared routing direction. A misalignment value is calculated for the first wire and the second wire, and a new routing placement is selected for the first wire based at least in part on the misalignment value. In some embodiments, all wires in various routings of a circuit design are checked for possible misalignment in order to improve slew performance via reduction of unnecessary vias.


Find Patent Forward Citations

Loading…