The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Jul. 25, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Yoshiro Shimojo, Yokohama, JP;

Masahisa Sonoda, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 23/528 (2006.01); H01L 27/1157 (2017.01); H01L 27/11582 (2017.01); H01L 23/522 (2006.01); H01L 27/11573 (2017.01); G11C 8/14 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 8/14 (2013.01); H01L 23/5226 (2013.01); H01L 27/1157 (2013.01);
Abstract

A memory device includes a memory region, a connection region, an interconnection layer and a circuit. The memory region includes electrode layers and semiconductor layers. The electrode layers are stacked in a first direction, and the semiconductor layers extend in the first direction through the electrode layers. The connection region is surrounded with the memory region, and includes an insulating body and contact plugs. The insulating body has a thickness in the first direction thicker than a stacked width in the first direction of the electrode layers, and the contact plugs extending in the first direction through the insulating body. The interconnection layer includes interconnections electrically connected respectively to the electrode layers and some of the semiconductor layers. The electrode layers and the insulating body are positioned between the circuit and the interconnection layer in the first direction.


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