The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Nov. 07, 2017
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kangguo Cheng, Schenectady, NY (US);

Juntao Li, Cohoes, NY (US);

Geng Wang, Stormville, NY (US);

Qintao Zhang, Mt Kisco, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); H01L 27/12 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H01L 29/861 (2006.01); H01L 21/8249 (2006.01); H01L 29/775 (2006.01); H01L 29/15 (2006.01); H01L 21/84 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 21/8249 (2013.01); H01L 27/1203 (2013.01); H01L 29/0657 (2013.01); H01L 29/0673 (2013.01); H01L 29/157 (2013.01); H01L 29/42392 (2013.01); H01L 29/66136 (2013.01); H01L 29/66439 (2013.01); H01L 29/66742 (2013.01); H01L 29/775 (2013.01); H01L 29/78618 (2013.01); H01L 29/78654 (2013.01); H01L 29/78696 (2013.01); H01L 29/861 (2013.01); H01L 29/8613 (2013.01); H01L 21/84 (2013.01); H01L 29/66545 (2013.01);
Abstract

Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.


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