The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Mar. 14, 2017
Applicant:

Alpha and Omega Semiconductor (Cayman) Ltd., Sunnyvale, CA (US);

Inventors:

Hongtao Gao, Shanghai, CN;

Jun Lu, San Jose, CA (US);

Ming-Chen Lu, Shanghai, CN;

Jianxin Ye, Shanghai, CN;

Yan Huo, Shanghai, CN;

Hua Pan, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); H01L 21/56 (2006.01); H01L 23/367 (2006.01); H01L 23/31 (2006.01); H01L 23/29 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 21/561 (2013.01); H01L 23/3672 (2013.01); H01L 23/3675 (2013.01); H01L 23/49503 (2013.01); H01L 23/49524 (2013.01); H01L 23/49541 (2013.01); H01L 23/49548 (2013.01); H01L 23/49562 (2013.01); H01L 23/49805 (2013.01); H01L 24/06 (2013.01); H01L 24/97 (2013.01); H01L 23/293 (2013.01); H01L 23/3121 (2013.01); H01L 24/05 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05553 (2013.01); H01L 2224/06051 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/131 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/291 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/371 (2013.01); H01L 2224/40247 (2013.01); H01L 2224/73263 (2013.01); H01L 2224/83805 (2013.01); H01L 2224/97 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.


Find Patent Forward Citations

Loading…