The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Apr. 11, 2017
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Zhenjiang Cui, San Jose, CA (US);

Xing Zhong, Foster City, CA (US);

Jie Liu, Sunnyvale, CA (US);

Linlin Wang, Fremont, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3213 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01J 37/32 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/32136 (2013.01); H01J 37/32357 (2013.01); H01J 37/32422 (2013.01); H01L 21/02071 (2013.01); H01L 21/28088 (2013.01); H01L 21/31138 (2013.01); H01L 21/32137 (2013.01); H01L 21/32139 (2013.01); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method for processing a semiconductor substrate is described herein. The method described herein includes generating fluorine radicals and ions, delivering the fluorine radicals through an ion blocker to a processing region, and removing one or more portions of a gate structure to expose one or more portions of a gate dielectric material disposed thereunder. The gate structure includes at least two ceramic or metal layers, and the gate dielectric material is made of a high-k dielectric material. A substrate having the gate structure and gate dielectric material formed thereon is disposed in the processing region, and the temperature of the substrate is maintained at about 60 degrees Celsius or higher. By etching the gate structure using fluorine radicals at a temperature greater or equal to 60 degrees Celsius, the at least two ceramic or metal layers have a flat cross sectional profile.


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