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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10504720 B1

PDFFull Text
Date of Patent:
Dec. 10, 2019

Filed:

Oct. 05, 2017

Etching using chamber with top plate formed of non-oxygen containing material

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

En-Ping Lin, Taoyuan, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Tzu-Chan Weng, Kaohsiung, TW;

Wen-Zhong Ho, Tainan, TW;

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

Nadine G Norton

Assistant Examiner:

Mahmoud Dahimene

Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/302 (2006.01); C23C 16/40 (2006.01); H01L 21/308 (2006.01); H01L 21/311 (2006.01); H01L 21/67 (2006.01); H01L 21/687 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02129 (2013.01); C23C 16/401 (2013.01); H01L 21/022 (2013.01); H01L 21/02008 (2013.01); H01L 21/02164 (2013.01); H01L 21/02271 (2013.01); H01L 21/02389 (2013.01); H01L 21/302 (2013.01); H01L 21/3081 (2013.01); H01L 21/31116 (2013.01); H01L 21/6719 (2013.01); H01L 21/68757 (2013.01); H01L 21/76224 (2013.01); H01L 21/76243 (2013.01);
Abstract

A method includes etching a first oxide layer in a wafer. The etching is performed in an etcher having a top plate overlapping the wafer, and the top plate is formed of a non-oxygen-containing material. The method further includes etching a nitride layer underlying the first oxide layer in the etcher until a top surface of a second oxide layer underlying the nitride layer is exposed. The wafer is then removed from the etcher, with the top surface of the second oxide layer exposed when the wafer is removed.

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