The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sean Lawless, Santa Cruz, CA (US);

Yaniv Frishman, Kiryat Ono, IL;

Paul Diefenbaugh, Portland, OR (US);

Vishal Sinha, Portland, OR (US);

Jason Tanner, Folsom, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 3/00 (2006.01); G06T 15/00 (2011.01); G06T 1/60 (2006.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06T 1/20 (2013.01); G06T 1/60 (2013.01); G06T 3/0093 (2013.01); G09G 2354/00 (2013.01); G09G 2360/10 (2013.01); G09G 2360/121 (2013.01); G09G 2360/18 (2013.01); G09G 2370/16 (2013.01);
Abstract

An apparatus and method for efficient rendering and transmission of video content in a virtual reality system. For example, one embodiment of an apparatus comprises: a first frame buffer to store image frames to be transmitted to a virtual reality apparatus; tile-based image rendering circuitry and/or logic to concurrently render multiple tiles of a first image frame, wherein tiles are categorized core tiles or a peripheral tiles; tile-based transmission circuitry and/or logic to transmit a first core tile rendered to the virtual reality apparatus before one or more remaining tiles have been rendered, the tile-based transmission circuitry and/or logic to continue to transmit one or more subsequently rendered core tiles following the first tile until all core tiles have been transmitted; and the tile-based transmission circuitry and/or logic to identify a subset of peripheral tiles to be transmitted based on first coordinate/offset data and to responsively transmit the subset of peripheral tiles.


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