The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Jun. 29, 2018
Applicant:

Samsung Electronics Co., Ltd., Suwoni-si, KR;

Inventors:

Sang-Uhn Cha, Yongin-si, KR;

Myeong-O Kim, Hwaseong-si, KR;

In-Woo Jun, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/10 (2006.01); G11C 29/52 (2006.01); H03M 13/29 (2006.01); G06F 3/06 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 11/1048 (2013.01); H03M 13/2906 (2013.01); G11C 29/52 (2013.01); G11C 2029/0411 (2013.01);
Abstract

Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data.


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