The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 10, 2019

Filed:

Sep. 30, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Monica Gupta, Hillsboro, OR (US);

Russell J. Fenger, Beaverton, OR (US);

Vijay Dhanraj, Beaverton, OR (US);

Deepak Samuel Kirubakaran, Hillsboro, OR (US);

Srividya Ambale, Hillsboro, OR (US);

Israel Hirsh, Kiryat Motzkin, IL;

Eliezer Weissmann, Haifa, IL;

Hisham Abu Salah, Majdal shams, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/50 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/50 (2013.01); G06F 9/5005 (2013.01); G06F 9/5027 (2013.01); G06F 9/5044 (2013.01); G06F 9/3009 (2013.01); G06F 2209/501 (2013.01);
Abstract

Technologies are provided in embodiments to dynamically bias performance of logical processors in a core of a processor. One embodiment includes identifying a first logical processor associated with a first thread of an application and a second logical processor associated with a second thread, obtaining first and second thread preference indicators associated with the first and second threads, respectively, computing a first relative performance bias value for the first logical processor based, at least in part, on a relativeness of the first and second thread preference indicators, and adjusting a performance bias of the first logical processor based on the first relative performance bias value. Embodiments can further include increasing the performance bias of the first logical processor based, at least in part, on the first relative performance bias value indicating a first performance preference that is higher than a second performance preference.


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