The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 10, 2019
Filed:
Oct. 23, 2013
Nvidia Corporation, Santa Clara, CA (US);
David Conrad Tannenbaum, Austin, TX (US);
Srinivasan (Vasu) Iyer, Austin, TX (US);
Stuart F. Oberman, Sunnyvale, CA (US);
Ming Y. Siu, Santa Clara, CA (US);
Michael Alan Fetterman, Boxborough, MA (US);
John Matthew Burgess, Austin, TX (US);
Shirish Gadre, Fremont, CA (US);
NVIDIA CORPORATION, Santa Clara, CA (US);
Abstract
A subsystem is configured to support a distributed instruction set architecture with primary and secondary execution pipelines. The primary execution pipeline supports the execution of a subset of instructions in the distributed instruction set architecture that are issued frequently. The secondary execution pipeline supports the execution of another subset of instructions in the distributed instruction set architecture that are issued less frequently. Both execution pipelines also support the execution of FFMA instructions as well as a common subset of instructions in the distributed instruction set architecture. When dispatching a requested instruction, an instruction scheduling unit is configured to select between the two execution pipelines based on various criteria. Those criteria may include power efficiency with which the instruction can be executed and availability of execution units to support execution of the instruction.