The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Sep. 14, 2017
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Mario Francisco Velez, San Diego, CA (US);

Niranjan Sunil Mudakatte, San Diego, CA (US);

Jonghae Kim, San Diego, CA (US);

Changhan Hobie Yun, San Diego, CA (US);

David Francis Berdy, San Diego, CA (US);

Shiqun Gu, San Diego, CA (US);

Chengjie Zuo, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03H 7/01 (2006.01); H01L 49/02 (2006.01); H01L 23/532 (2006.01); H03H 3/00 (2006.01); H01L 27/01 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 21/321 (2006.01); H01L 21/768 (2006.01); H03H 1/00 (2006.01);
U.S. Cl.
CPC ...
H03H 7/0115 (2013.01); H01L 23/5223 (2013.01); H01L 23/5227 (2013.01); H01L 23/5283 (2013.01); H01L 23/53257 (2013.01); H01L 27/016 (2013.01); H01L 28/10 (2013.01); H01L 28/60 (2013.01); H03H 3/00 (2013.01); H01L 21/3212 (2013.01); H01L 21/7684 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76871 (2013.01); H01L 21/76877 (2013.01); H03H 2001/0085 (2013.01);
Abstract

An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.


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