The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Mar. 20, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Satoshi Tsukiyama, Yokohama, JP;

Yoichiro Kurita, Minato, JP;

Hideo Aoki, Yokohama, JP;

Kazushige Kawasaki, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/04 (2014.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01); H01L 25/11 (2006.01); H01L 25/18 (2006.01); H01L 25/075 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 25/0657 (2013.01); H01L 25/043 (2013.01); H01L 25/074 (2013.01); H01L 25/0756 (2013.01); H01L 25/117 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06555 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/06586 (2013.01); H01L 2225/06589 (2013.01);
Abstract

A semiconductor device according to an embodiment includes a first memory chip having a first front surface and a first back surface and having a first memory circuit provided on the first front surface side; a second memory chip having a second front surface and a second back surface facing the first front surface, having a second memory circuit provided on the second front surface side, and being electrically connected to the first memory chip; and a logic chip having the first memory chip provided between the logic chip and the second memory chip, having a third front surface and a third back surface, having a logic circuit provided on the third front surface side, and being electrically connected to the first memory chip.


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