The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Dec. 31, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Russell S. Aoki, Tacoma, WA (US);

Casey G. Thielen, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 25/18 (2006.01); H01L 23/544 (2006.01); H05K 1/18 (2006.01); H05K 3/34 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 23/32 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/32 (2013.01); H01L 23/544 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H05K 1/181 (2013.01); H05K 3/341 (2013.01); H05K 3/3494 (2013.01); H01L 2223/54426 (2013.01); H05K 2201/10378 (2013.01); H05K 2201/10522 (2013.01); H05K 2201/10734 (2013.01); H05K 2203/11 (2013.01);
Abstract

Configurable semiconductor packages and processes to attain a defined configuration are provided. A configurable semiconductor package includes a base semiconductor package including a semiconductor die mounted on a surface of a package substrate. An expansion package can be mechanically coupled to a mounting member. The expansion package includes a second package substrate and one or more second semiconductor dies that can be surface mounted to the second package substrate. The second package substrate include an array of interconnects that permit coupling (mechanically and/or electrically) the second semiconductor die(s) to the package substrate of the base semiconductor package. The mounting member can mechanically attach to the base semiconductor package, resulting in a package assembly that has the array of interconnects adjacent to another array of interconnects in the package substrate of the base semiconductor package. The expansion package can be coupled to the base semiconductor package via the interconnects, providing expanded functionality relative to the functionality of the base semiconductor package.


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