The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

May. 08, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Siva Prakash Gurrum, Allen, TX (US);

Manu J Prakuzhy, Allen, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 29/78 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49503 (2013.01); H01L 21/4828 (2013.01); H01L 23/49582 (2013.01); H01L 24/48 (2013.01); H01L 24/83 (2013.01); H01L 29/7395 (2013.01); H01L 29/7802 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/83385 (2013.01); H01L 2224/83815 (2013.01);
Abstract

A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.


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