The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Aug. 23, 2018
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Kenichi Arakawa, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); H01L 23/528 (2006.01); H01L 27/115 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 16/0483 (2013.01); H01L 23/528 (2013.01); H01L 27/115 (2013.01);
Abstract

A semiconductor memory device facilitating an area efficiency of a page buffer/sense circuit and suppressing erroneous operation due to capacitive coupling between wires is provided. The flash memoryof the disclosure includes a memory cell arrayand a page buffer/sense circuit. The memory cell arrayincludes a plurality of memory cells. The page buffer/sense circuitholds data read from a page selected by the memory cell arrayor holds data to be programmed to a page selected by the memory cell array. The page buffer/sense circuitis arranged in n columns×m segments within one pitch in a row direction defined by p number of bit lines extending from the memory cell array. n is an integer of 2 or more then 2, and m is an integer of 2 or more then 2.


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