The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Feb. 07, 2018
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Kazutaka Takizawa, Yokohama, JP;

Masaaki Niijima, Machida, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/14 (2006.01); G11C 16/04 (2006.01); G11C 16/16 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0483 (2013.01); G11C 16/16 (2013.01); G11C 16/3445 (2013.01);
Abstract

According to one embodiment, a memory system includes a memory and controller. The controller repeatedly performs an erase voltage application process for data stored in a target area in the memory. The controller performs an erase verification process for determining whether the erase is successful using erase verification voltage. The controller determines whether an erase time is longer than a first threshold value. The controller sets the target area to a use prohibition state when the erase time is longer than the first threshold value.


Find Patent Forward Citations

Takizawa, Kazutaka. (2019). Memory system controlling data erase for nonvolatile memory and control method for erasing data (U.S. Patent No. 10497446). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10497446

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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