The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2019
Filed:
Apr. 10, 2017
Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;
Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;
Zheng Fang Liu, Shanghai, CN;
Xue Li, Shanghai, CN;
Abstract
A CMP simulation method includes inputting a chip pattern layout including a plurality of graphic patterns, partitioning the chip pattern layout into targeting grids including a plurality of surrounding grids, and then calculating grid geometry characteristics of the targeting grids. The method also includes generating shifted grids by shifting the targeting grids, calculating weighted average grid geometry characteristics of the targeting grids and the shifted grids, and locating first hot spots on the chip pattern layout by performing a CMP simulation based on the grid geometry characteristics of the targeting grids. Further, the method includes generating optimized grid geometry characteristics by modifying the grid geometry characteristics of the targeting grids based on the weighted average grid geometry characteristics and the defined first hot spots, and then locating second hot spots on the chip pattern layout by performing the CMP simulation based on the optimized grid geometry characteristics.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile