The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Jul. 05, 2016
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Kumar Chidhambara Keshavan, Medford, MA (US);

Ambrish Kant Varma, Chelmsford, MA (US);

Hui Qi, Shanghai, CN;

Kenneth Robert Willis, Matthews, NC (US);

Xuegang Zeng, Westborough, MA (US);

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 11/07 (2006.01); G06F 21/51 (2013.01);
U.S. Cl.
CPC ...
G06F 17/5009 (2013.01); G06F 17/5022 (2013.01); G06F 17/5045 (2013.01); G06F 11/0784 (2013.01); G06F 17/5081 (2013.01); G06F 21/51 (2013.01);
Abstract

The present disclosure relates to non-linear systems associated with an electronic circuit design. Embodiments may include identifying the non-linear system associated with the electronic circuit design and determining a degree of severity of non-linearity of the non-linear system associated with the electronic circuit design. If the degree of severity is less than a predefined threshold, embodiments may further include receiving a random input pattern and deriving a single impulse response characterization, wherein the random input pattern is based upon, at least in part, an electronic circuit simulation associated with the electronic circuit design.


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