The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 03, 2019

Filed:

Mar. 03, 2014
Applicants:

Michael Johnston, Paisley, GB;

Alan Devine, Paisley, GB;

Alistair Paul Robertson, Glasgow, GB;

Manfred Thanner, Neubiberg, DE;

Inventors:

Michael Johnston, Paisley, GB;

Alan Devine, Paisley, GB;

Alistair Paul Robertson, Glasgow, GB;

Manfred Thanner, Neubiberg, DE;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/14 (2006.01); G06F 12/02 (2006.01); G06F 21/00 (2013.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1475 (2013.01); G06F 12/0284 (2013.01); G06F 21/00 (2013.01); G06F 12/1441 (2013.01); G06F 15/7807 (2013.01); G06F 2212/1052 (2013.01);
Abstract

A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.


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