The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 03, 2019
Filed:
Nov. 15, 2017
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 7/00 (2006.01); G03F 1/36 (2012.01); H01L 21/027 (2006.01); H01L 21/66 (2006.01); G03F 1/80 (2012.01); G03F 7/16 (2006.01); G03F 7/20 (2006.01); G03F 7/38 (2006.01); G03F 7/26 (2006.01); G03F 1/78 (2012.01);
U.S. Cl.
CPC ...
G03F 1/36 (2013.01); G03F 1/78 (2013.01); G03F 1/80 (2013.01); G03F 7/16 (2013.01); G03F 7/20 (2013.01); G03F 7/26 (2013.01); G03F 7/38 (2013.01); G06F 17/5009 (2013.01); G06F 17/5081 (2013.01); H01L 21/0277 (2013.01); H01L 22/20 (2013.01); G06F 2217/12 (2013.01);
Abstract
The present disclosure provides an integrated circuit (IC) method in accordance with some embodiments. The method includes building a mask model to simulate a mask image and a compound lithography computational model to simulate a wafer pattern; calibrating the mask model using a measured mask image; calibrating the compound lithography computational model using a measured wafer data and the calibrated mask model; and performing an optical proximity correction (OPC) process to an IC pattern using the calibrated compound computational model, thereby generating a mask pattern for mask fabrication.